Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

Y. Monnet (1) , Marc Renaudin (1) , Régis Leveugle (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection.

Mots clés: hardening techniques.

Mots clés: Asynchronous circuits; data encryption standard; fault attacks; hardening techniques; quasi-delay insensitive

Domaines: Micro et nanotechnologies/Microélectronique

Y. Monnet, Marc Renaudin, Régis Leveugle. Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Transactions on Computers, 2006, Volume: 55 Issue: 9, pp.1104 - 1115. ⟨10.1109/TC.2006.143⟩. ⟨hal-00105247⟩