An Asynchronous DES Crypto-Processor Secured against Fault Attacks

Y. Monnet (1) , Marc Renaudin (1) , Régis Leveugle (1) , S. Dumont (1) , Ghislain Fraidy Bouesse (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents a hardened asynchronous DES crypto-processor against fault attacks. A fault attack consists in causing an intentional temporary dysfunction of a circuit by injecting faults in its combinational or sequential parts. This failure enables hackers to access protected memory areas or secret information like cryptographic keys. An analysis of the behavior of VLSI Quasi Delay Insensitive (QDI) asynchronous circuits in the presence of faults shows that they are attractive to design robust systems. In this paper, an asynchronous reference DES architecture is described. Then hardening techniques are proposed and applied at the design time to significantly harden the DES architecture with a very low area overhead and a reasonable performance penalty.

Mots clés: asynchronous

Domaines: Micro et nanotechnologies/Microélectronique

Y. Monnet, Marc Renaudin, Régis Leveugle, S. Dumont, Ghislain Fraidy Bouesse. An Asynchronous DES Crypto-Processor Secured against Fault Attacks. 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19, 2005, Perth, Australia. ⟨hal-00102771⟩