FLPA: A New Methodology for Processor Power Characterization
Résumé
This thesis demonstrates that power estimation of a C-code without compilation is possible with the help of a functional approach. The Functional Level Power analysis (FLPA) estimation method was initially developed and validated at the assembly-level with a maximum error of 3.5% against measurements. It includes two steps: the model definition and the estimation process. The model definition provides a complete power model of the processor with algorithmic and configuration parameters as inputs; it has been built from a functional analysis of the processor dissipation combined with a reduced set of physical measurements. This model includes important phenomena for the power consumption, like pipeline stalls and cache misses. The estimation process analyzes the code and extracts the required parameters. For the C-level power estimation, we propose to use the same power model of the processor; but, in this case, some algorithmic parameters are now predicted from the C code rather than exactly computed from the compiled code. Then, a first estimation is possible with only elementary architectural considerations about the target; this estimation provides the maximum and minimum bounds for the power consumption. By adding simple assumptions on data placement, our method provides estimates with an average error of 4% against physical measurements. Even at the early stage of the design process where some parameters are still unknown, estimation results are gathered on a consumption map on which the algorithm profile can be checked with the application constraint. The method was applied on the Texas Instruments C6x for which a complete power model has been developed. This processor was chosen for its complex architecture: a deep pipeline (up to 11 stages), VLIW instructions set, and parallelism capabilities (up to 8 instructions in parallel). Its internal program memory can be used in cache mode. It also contains an External Memory Interface (EMIF), used to load data and program from the external memory. Several real life classical digital signal processing algorithms where evaluated: a FIR filter, a FFT, a LMS filter, a Discrete Wavelet Transform (DWT) with two different image sizes (64*64 and 512*512), and an Enhanced Full Rate (EFR) vocoder for GSM. The maximum gap between our estimations and the measurements is 6%.