Power Consumption Modeling and Characterization of the TI C6201
Résumé
A new approach to characterize the power dissipation on complex digital signal processors (DSP) is proposed. The processor model relies on an initial Functional Level Power Analysis of the target, together with a characterization that qualifies the more significant architectural and algorithmic parameters for the power dissipation. Whereas the classical instruction level method is limited for complex architectures, our functional model can take into account deep pipelined, superscalar and hierarchical memory architectures. The parameters are obtained through a simple profiling of the assembly code. The detailed model of the TI C6201 is extensively presented; its validation is proposed through several digital signal-processing algorithms with a maximum error of 4% against measurements. This model is also used to express the impact of the architecture complexity of this superpipeline and superscalar DSP to the global power consumption. This high-level approach is easily extended to other targets, through the generic power model, providing a similar estimation accuracy.