A channelless layout for multilevel synthesis with compiled cells

G. Saucier (1, 2) , Régis Leveugle (1, 2) , P. Abouzeid (1)

1 CSI - CSI, INPG, Grenoble
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

A novel method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented. A compiled cell is the implementation on silicon of a lexicographical factorized Boolean expression. How a compiled cell is obtained automatically from the Boolean expression (layout synthesis) is recalled, and the rewriting of Boolean functions in terms of compiled cells is addressed. This approach leads to a dense and regular layout by abutment of compiled cells. The wiring channels are thus suppressed.

Mots clés: channelless-layout; multilevel-synthesis; compiled-cells; CMOS-; lexicographical-factorized-Boolean-expression; layout-synthesis; Boolean-functions; regular-layout; abutment-; wiring-channels

Domaines: Micro et nanotechnologies/Microélectronique

G. Saucier, Régis Leveugle, P. Abouzeid. A channelless layout for multilevel synthesis with compiled cells. Proceedings.-1989-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.89CH2794-6, 1989, Cambridge, MA, United States. pp.35-8, ⟨10.1109/ICCD.1989.63323⟩. ⟨hal-00015347⟩