Highly wireable multilevel synthesis with compiled cells

Régis Leveugle (1, 2) , G. Saucier (1, 2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 CSI - CSI, INPG, Grenoble

An original method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented here. A compiled cell is the implementation on silicon of a `lexicographical' factorized Boolean expression. It is recalled how a compiled cell is obtained automatically from the Boolean expression. The rewriting of Boolean functions in terms of compiled cells is then addressed. This leads to a dense and regular layout by abutment of compiled cells. The wiring channels are so suppressed.

Mots clés: compiled-cells; optimized-multilevel-synthesis; CMOS-circuitry; factorized-Boolean-expression; rewriting-; regular-layout; abutment-; wiring-channels

Domaines: Micro et nanotechnologies/Microélectronique

Régis Leveugle, G. Saucier. Highly wireable multilevel synthesis with compiled cells. Logic-and-Architecture-Synthesis-for-Silicon-Compilers.-Proceedings-of-the-International-Workshop, 1989, Grenoble, France. pp.37-52. ⟨hal-00015340⟩