Fault injection in VHDL descriptions and emulation

Régis Leveugle (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It is proposed to carry out such an analysis using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design. Injection of erroneous transitions is automated and results are presented.

Mots clés: VHDL-descriptions; potential-faulty-behaviors; probability-; RT-level-VHDL-descriptions; hardware-prototyping; erroneous-transitions; fault-injection

Domaines: Micro et nanotechnologies/Microélectronique

Régis Leveugle. Fault injection in VHDL descriptions and emulation. Proceedings-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems, 2000, Yamanashi, Japan. pp.414-19, ⟨10.1109/DFTVS.2000.887182⟩. ⟨hal-00015057⟩