A low-cost hardware approach to dependability validation of IPs

Régis Leveugle (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

It has been recognized that analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of transient faults. It has been proposed to carry out such an analysis using fault injections in a hardware prototype of the circuit under design. This paper reports on a low cost environment using such a flow. A simple FPGA-based development board is used to emulate the circuit and the execution results are analysed on a PC computer. A generic, scalable, approach is proposed to overcome the limitations of such a simple set-up. Such an environment can for example allow a designer to perform efficient and low cost dependability analyses for IP blocks.

Mots clés: low-cost-hardware-approach; dependability-validation; IP-blocks; re-usable-components; potential-faulty-behaviors; probability-; transient-faults; fault-injections; circuit-under-design; FPGA-based-development-board

Domaines: Micro et nanotechnologies/Microélectronique

Régis Leveugle. A low-cost hardware approach to dependability validation of IPs. Proceedings-2001-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems, 2001, San Francisco, CA, United States. pp.242-9, ⟨10.1109/DFTVS.2001.966776⟩. ⟨hal-00015048⟩