Design of a GaAs redundant divider

I. Moussa (1) , A. Skaf (1) , A. Guyot (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Presents a fast combinatorial circuit for performing division Q:=A+D. High speed is achieved by a new algorithm implemented in gallium arsenide (GaAs). An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delay-units, with n/sup 2/ add/sub cells (called tail) driven by n controller cells (called head). The divider has been implemented by using a buffering technique and a full custom layout methodology, which are well suited for high performance design in GaAs direct coupled FET Logic (DCFL).

Mots clés: combinatorial-circuit; n-bit-divider; n-bit-quotient; NOR-gate-delay-units; controller-cells; buffering-technique; full-custom-layout-methodology; direct-coupled-FET-Logic

Domaines: Micro et nanotechnologies/Microélectronique

I. Moussa, A. Skaf, A. Guyot. Design of a GaAs redundant divider. IFIP-Transactions-A-Computer-Science-and-Technology, 1994, A-42:, pp.63-72. ⟨hal-00014956⟩