Formal verification of microprogrammed architectures

D. Borrione (1) , P. Camurati (2) , J.-L. Paillet (2) , P. Prinetto (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 Polito - Politecnico di Torino = Polytechnic of Turin

The paper presents the application of formal verification techniques to a real microprocessor. The device is described and verified resorting to a functional model. A methodology which can be used in a wide number of cases is also presented.

Mots clés: microprogrammed-architectures; formal-verification-techniques; functional-model

Domaines: Micro et nanotechnologies/Microélectronique

D. Borrione, P. Camurati, J.-L. Paillet, P. Prinetto. Formal verification of microprogrammed architectures. CAD-&-CG-'89-Beijing.-Proceedings-of-International-Conference-on-Computer-Aided-Design-and-Computer-Graphics., 1989, Beijing, China. pp.562-7. ⟨hal-00014299⟩