Quiescent current estimation based on quality requirements
Abstract
Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, for instance, minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution. This approach is exemplified with the characterization of an in-house developed cell library.