Easily testable carry-save multipliers with respect to path delay faults

Th. Haniotakis (1) , H.-T. Vergos (1) , Y. Tsiatouhas (1) , D. Nikolos (1) , M. Nicolaidis (2, 3)

1 Department of Computer Engineering and Informatics [Patras]
2 IROC TECHNOLOGIES - iROc Technologies
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

In this paper we propose the design of an easily testable, with respect to path delay faults, n*m carry-save multiplier (CSM) and give a path selection method such that all the selected paths for testing are Single Path Propagating Hazard Free Robustly Testable (SPP-HFRT). Only three additional test inputs are required while the hardware overhead is very small and the delay overhead negligible.

Mots clés: carry-save-multipliers; path-delay-faults; path-selection-method; single-path-propagating-hazard-free-robustly-testable; SPP-HFRT

Domaines: Micro et nanotechnologies/Microélectronique

Th. Haniotakis, H.-T. Vergos, Y. Tsiatouhas, D. Nikolos, M. Nicolaidis. Easily testable carry-save multipliers with respect to path delay faults. ECS'99.-Proceedings-of-the-2nd-Electronics-Circuits-and-Systems-Conference, 1999, Bratislava, Slovakia. pp.13-16. ⟨hal-00013748⟩