Design of SEU-hardened CMOS memory cells: the HIT cell

D. Bessot (1) , Raoul Velazco (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

A memory cell, called HIT cell (heavy ion tolerant cell), designed to be SEU-immune is presented. Compared to previously reported design hardened solutions, the HIT cell is less SEU-sensitive, features better electrical performances and consumes less silicon area.

Mots clés: HIT-cell; SEU-immune; design-hardened-solutions; SEU-sensitive; electrical-performances; silicon-area; single-event-upset

Domaines: Micro et nanotechnologies/Microélectronique

D. Bessot, Raoul Velazco. Design of SEU-hardened CMOS memory cells: the HIT cell. European Conference on Radiation and its Effects on Components and Systems (RADECS'93), Sep 1993, Saint-Malo, France. pp.563-570. ⟨hal-00008260⟩