SEU testing of a novel hardened register implemented using standard CMOS technology

Thierry Monnier (1) , Fernand-Michel Roche (2) , J. Cosculluela (3) , Raoul Velazco (4)

1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
4 IMAG - Institut d'Informatique et de Mathématiques Appliquées de Grenoble

A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption.

Mots clés: SEU-testing; hardened-register; standard-CMOS-technology; memory-structure; heavy-ion-tests; SEU-robustness; LET-threshold; cross-section; power-consumption

Domaines: Micro et nanotechnologies/Microélectronique

Thierry Monnier, Fernand-Michel Roche, J. Cosculluela, Raoul Velazco. SEU testing of a novel hardened register implemented using standard CMOS technology. IEEE Transactions on Nuclear Science, 1999, 46 (6), pp.1440-1444. ⟨10.1109/23.819105⟩. ⟨hal-00008234⟩