Deep submicron CMOS technologies for the LHC experiments

P. Jarron (1) , G. Anelli (1) , T. Calin (1) , J. Cosculluela (1) , M. Campbell (1) , M. Delmastro (1) , F. Faccio (1) , A. Giraldo (1) , E. Heijne (1) , K. Kloukinas (1) , M. Letheren (1) , M. Nicolaidis (2) , P. Moreira (1) , A. Paccagnella (1) , A. Marchioro (1) , W. Snoeys (1) , Raoul Velazco (3)

1 CERN [Genève]
2 IROC TECHNOLOGIES - iROc Technologies
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed

Mots clés: LHC-experiments; radiation-hard-ASICs; total-ionising-dose; enclosed-NMOS-devices; guard-rings; deep-submicron-CMOS-technologies; circuit-level; transistor-level; design-implications; single-event-effects; effective-W-L; radiation-tolerance-design; aspect-ratio; radiation-tolerant-standard-cell-library; detectors-front-end-electronics; 0.25-mum

Domaines: Micro et nanotechnologies/Microélectronique

P. Jarron, G. Anelli, T. Calin, J. Cosculluela, M. Campbell, et al.. Deep submicron CMOS technologies for the LHC experiments. Nuclear Physics B, 1999, Aug. 1999; 78, pp.625-34. ⟨hal-00008232⟩