Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures

M. Rebaudengo (1) , M.S. Reorda (2) , M. Violante (1) , P. Cheynet (2) , B. Nicolescu (2) , Raoul Velazco (2)

1 DAUIN - Dipartimento di Automatica e Informatica [Torino]
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper deals with a method able to provide a microprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent of the adopted platform.

Mots clés: software-fault-tolerance-technique; RISC-based-architectures; CISC-based-architectures; microprocessor-based-system; safety-capabilities; source-code-modification; transformations-; fault-Injection-experiments; CISC-processors; RISC-processors; data-errors; code-errors

Domaines: Micro et nanotechnologies/Microélectronique

M. Rebaudengo, M.S. Reorda, M. Violante, P. Cheynet, B. Nicolescu, et al.. Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures. 2000, pp.17-21, ⟨10.1109/OLT.2000.856606⟩. ⟨hal-00008226⟩