Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

Raoul Velazco (1) , S. Rezgui (1) , R. Ecoffet (1, 2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 CNES - Centre National d'Études Spatiales [Toulouse]

This paper investigates an approach to study the effects of upsets on the operation of microprocessor-based digital architectures. The method is based on the injection of bit-flips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy.

Mots clés: error-rate; microprocessor-; digital-architecture; code-emulating-upset; bit-flip-injection; 80C51-microcontroller; 320C50-digital-signal-processor; radiation-environment

Domaines: Micro et nanotechnologies/Microélectronique

Raoul Velazco, S. Rezgui, R. Ecoffet. Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection. IEEE Transactions on Nuclear Science, 2000, Dec. 2000; Volume: 47 Issue: 6 Part 3, pp.2405-2411. ⟨10.1109/23.903784⟩. ⟨hal-00008219⟩