Efficiency of transient bit-flips detection by software means: a complete study

B. Nicolescu (1) , P. Peronnard (2) , Raoul Velazco (2) , B.Y. Savaria (1)

1 EPM - École Polytechnique de Montréal
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This-paper characterizes the effectiveness of an error detection technique that addresses transient faults induced by the environment (radiation, EMC) in processor-based architectures. Experimental results obtained from fault injection sessions performed on two platforms built around a 32-bit digital signal processor and an 8-bit microcontroller, provide objective figures about the efficiency of the proposed approach.

Mots clés: fault-tolerance; software-error-detection-technique; safety-critical-applications; transient-bit-flip-detection-efficiency; environment-induced-transient-faults; radiation-induced-faults; EMC-induced-faults; processor-based-architectures; fault-injection; digital-signal-processor; microcontroller-; single-event-upset; SEU-; 32-bit; 8-bit

Domaines: Micro et nanotechnologies/Microélectronique

B. Nicolescu, P. Peronnard, Raoul Velazco, B.Y. Savaria. Efficiency of transient bit-flips detection by software means: a complete study. 18th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems, 2003, France. pp.377-384, ⟨10.1109/DFTVS.2003.1250134⟩. ⟨hal-00008193⟩