Impact of data cache memory on the single event upset-induced error rate of microprocessors

F. Faure (1) , Raoul Velazco (2) , M. Violante (2) , M. Rebaudengo (2) , M.S. Reorda (2)

1 IASF-MI - Istituto di Astrofisica Spaziale e Fisica Cosmica - Milano
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper.

Mots clés: data-cache-memory; single-event-upset-induced-error-rate; microprocessors-

Domaines: Micro et nanotechnologies/Microélectronique

F. Faure, Raoul Velazco, M. Violante, M. Rebaudengo, M.S. Reorda. Impact of data cache memory on the single event upset-induced error rate of microprocessors. IEEE Transactions on Nuclear Science, 2003, Volume: 50 Issue: 6 Part 1, pp.2101 - 2106. ⟨10.1109/TNS.2003.821824⟩. ⟨hal-00008188⟩