Unifying memory and processor wrapper architecture in multiprocessor SoC design

Ferid Gharsalli (1) , D. Lyonnard (1) , A. Meftali , Frédéric Rousseau (1) , A.A. Jerraya (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. this approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.

Mots clés: multiprocessor-system-on-chip-design; application-specific; System-on-Chip; system-architecture; wrapper-; memory-wrapper-generation

Domaines: Micro et nanotechnologies/Microélectronique

Ferid Gharsalli, D. Lyonnard, A. Meftali, Frédéric Rousseau, A.A. Jerraya. Unifying memory and processor wrapper architecture in multiprocessor SoC design. 15th International Symposium on System Synthesis (ISSS'02), 2002, Kyoto, Japan. pp.26-31, ⟨10.1109/ISSS.2002.1227147⟩. ⟨hal-00008060⟩