Address calculation for retargetable compilation and exploration of instruction-set architectures

C. Liem (1) , P. Paulin (2) , A.A. Jerraya (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 CENTRAL R&D SGS - Thomson Microelectron

The advent of parallel executing address calculation units (ACUs) in digital signal processor (DSP) and application specific instruction-set processor (ASIP) architectures has made a strong impact on an application's ability to efficiently access memories. Unfortunately, successful compiler techniques which map high-level language data constructs to the addressing units of the architecture have lagged far behind. Since access to data is often the most demanding task in DSP, this mapping can be the most crucial function of the compiler. This paper introduces a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. The ArrSyn utility is designed to be used either as an enhancement to an existing dedicated compiler or as an aid for architecture exploration.

Mots clés: parallel-executing-address-calculation-units; digital-signal-processor; application-specific-instruction-set-processor-architectures; high-level-language-data-constructs; addressing-units; compiler-; array-references; traversals-; ArrSyn-utility; dedicated-compiler; retargetable-compilation; instruction-set-architectures

Domaines: Micro et nanotechnologies/Microélectronique

C. Liem, P. Paulin, A.A. Jerraya. Address calculation for retargetable compilation and exploration of instruction-set architectures. 1996, pp.597-600, ⟨10.1145/240518.240631⟩. ⟨hal-00008023⟩