Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy

Lorena Anghel (1) , D. Alexandrescu (1) , M. Nicolaidis (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 IROC TECHNOLOGIES - iROc Technologies

IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Manufacturing testing and periodic testing cannot cope with soft errors. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation of a new soft error tolerance technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluation of the proposed fault-tolerance technique were made using in-house tools realized around an event driven simulator. The obtained results show that tolerance of soft errors can be achieved at low cost.

Mots clés: redundancy; fault tolerant computing; performance evaluation; timing; transient analysis; integrated circuit reliability; errors; logic design; integrated logic circuits

Domaines: Micro et nanotechnologies/Microélectronique

Lorena Anghel, D. Alexandrescu, M. Nicolaidis. Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000, Manaus, Amazonas, Brazil. pp.237-42, ⟨10.1109/SBCCI.2000.876036⟩. ⟨hal-00005833⟩