Robustness of circuits under delay-induced faults : test of AES with the PAFI tool

Olivier Faurax (1) , Laurent Freund (1) , Assia Tria (2) , Traian Muntean (3) , Frédéric Bancel (4)

1 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
2 ERC CEA / EMSE - Équipe de Recherche Commune CEA - EMSE (SESAM : Secured Embedded Systems And Microelectronics)
3 LGI - IMAG - Laboratoire de Génie Informatique
4 ST-ROUSSET - STMicroelectronics [Rousset]

Security of cryptographic circuits is a major concern. Fault attacks are a mean to obtain critical information with the use of physical disturbance and cryptanalysis. We propose a methodology and a tool to analyse the robustness of circuit under faults induced by a delay. We tested a circuit implementing AES and showed that delay faults can permit to perform known fault attacks.

Mots clés: Security; Fault attacks; AES

Domaines: Micro et nanotechnologies/Microélectronique

Olivier Faurax, Laurent Freund, Assia Tria, Traian Muntean, Frédéric Bancel. Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. 13th IEEE International On-Line Testing Symposium IOLTS 2007, Jul 2008, Heraklion, France. pp.185-186, ⟨10.1109/IOLTS.2007.57⟩. ⟨emse-00504707⟩