The new 3-satge, low dissipation digital filter of the ALMA correlator
Résumé
The main goal of this study is to reduce the power dissipation of the 2-stage digital filter used in the ALMA Correlator system. This has been achieved by optimizing the number of FPGA logic elements used for the filter implementation. We have investigated the implementation of various structures based on the Cascaded Integrator Comb (CIC) filter in order to replace the present first filter stage, a 32-time demultiplexed input decimation filter. We conclude that a CIC filter cascaded with a quarter-band filter significantly improves the overall power dissipation and thus the FPGA thermal behaviour and reliability. This new design results in a significant improvement (nearly 25%) in the dissipation of each one of the ALMA filter cards.