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Article Dans Une Revue Journal de Physique Colloques Année : 1989

INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS

J. Kölzer
  • Fonction : Auteur
J. Otto
  • Fonction : Auteur

Résumé

Chip verification and failure analysis during the design evaluation of very large scale integrated (VLSI) devices call for highly accurate internal analysis methods. After having characterized the first silicon by automated functional testing, classification and statistical analysis can be carried out : In this way a rough electrical evaluation of the material under investigation can be made. Further clues to a faulty device behavior can only be obtained by internal measurements. Serious malfunctions of circuit blocks and internally traced signals can easily be detected by scanning electron beam operation, making use of the qualitative voltage contrast ; several individual modes of operation are known, such as voltage coding, logic-state mapping and frequency tracing and mapping, for example [1]. While electron beam testing is indispensable for nondestructive and nonloading measurements on submicron interconnection lines [2] mechanical probing can be used for waveform measurements on less critical geometries, too [3]. Hot spot detection (liquid crystal thermography) can be a very helpful and also nondestructive analysis tool for localization of defective areas [4]. Areas of high power dissipation on the chip can easily be located, because they appear as black spots when the IC-surface is viewed through crossed polarizers in the optical microscope. In situations where there does not appear to exist a direct link between the occurance of hot spots and the actual defective area, the laser is a powerful tool, solving this problem by subsequent cutting of metallization lines [5]. Additionally defect identification often calls for destructive methods like wet chemical and plasma etching followed by light or SEM inspection.

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jpa-00229658 , version 1 (04-02-2008)

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J. Kölzer, J. Otto. INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS. Journal de Physique Colloques, 1989, 50 (C6), pp.C6-173-C6-173. ⟨10.1051/jphyscol:1989627⟩. ⟨jpa-00229658⟩

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