A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

Nicolas Monnereau (1) , Fabrice Caignet (1) , David Trémouilles (2) , Nicolas Nolhier (1) , Marise Bafleur (1)

1 LAAS-ESE - Équipe Énergie et Systèmes Embarqués
2 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie

A system level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.

Keywords: electrostatic discharge; system level ESD; behavioral modeling; VHDL-AMS

Domains: Micro and nanotechnologies/Microelectronics

Nicolas Monnereau, Fabrice Caignet, David Trémouilles, Nicolas Nolhier, Marise Bafleur. A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis. IEEE Transactions on Electromagnetic Compatibility, 2013, 55 (1), pp.45-57. ⟨10.1109/TEMC.2012.2208973⟩. ⟨hal-00941876⟩