A VHDL-AMS Simulation Methodology for Transient Supply Current Extraction

Richard Perdriau (1) , Damien Lambert , Anne-Marie Trullemans (2) , Mohamed Ramdani (1)

1 ESEO-EMC
2 DICE - MLG - Dispositifs Intégrés et Circuits Electroniques Machine Learning Group

Transient supply current extraction plays a very important role in estimating performance level in the IC ElectroMagnetic Compatibility (EMC) field. Until now, average supply current estimations have been carried out for low-power design purposes, but they do not take into account high-frequency emission created by dI/dt effects. As far as complex circuits such as microcontrollers (uC) are concerned, transistor-level (SPICE-based) simulation leads to very long CPU times, mainly because of memory arrays which often represent more than 80 % of the transistors in a uC. VHDL-AMS simulators like ADVance-MS (Mentor Graphics) allow the designer to describe memories at the behavioral level while keeping the microcontroller core itself at the structural level. Moreover, seeing that very high accuracy is not needed for EMC studies, the use of much faster but less accurate simulation tools like Mach (Mentor Graphics) is made possible. In the first step, the dynamic supply current consumption of the uC core alone is simulated by coupling purely digital (VITAL) VHDL models for Flash and RAM blocks (providing only code and data) to the transistor-level core. The next step consists in adding VHDL-AMS behavioral models of the consumption of the memory blocks themselves to the VITAL descriptions. These models may take into account the addressing scheme and a statistical estimation of the contents of the arrays. This allows us to deal with the whole microcontroller without dramatically increasing simulation time. Furthermore, this method should be applicable to on-chip caches for more complex microcontrollers. The whole equivalent supply current generator may then be included in the recent Integrated Circuit Electromagnetic Model (ICEM), allowing EMC designers to predict conducted emission levels before sending the chip to the foundry. Moreover, this method should indicate how much executable code may influence conducted emission, and if so, help to write EMC-friendly software. Test chips and boards have been designed in order to compare simulation results to real-world measurements (current pulses on power supply networks). This work is supported by the MESDIE project.

Mots clés: EMC; IC; emission; immunity; susceptibility; modelling; IEC; integrated circuit; electromagnetic compatibility

Domaines: Micro et nanotechnologies/Microélectronique

Richard Perdriau, Damien Lambert, Anne-Marie Trullemans, Mohamed Ramdani. A VHDL-AMS Simulation Methodology for Transient Supply Current Extraction. 3rd International Workshop on Electromagnetic Compatibility of Integrated Circuits, Nov 2002, Toulouse, France. pp.99-104. ⟨hal-00526234⟩