Simulation-based validation of VHDL descriptions using constraints logic programming
Résumé
This paper presents a simulation based validation approach for test vectors generation. We suggest to borrow techniques used successfully in the software testing and constraints logic programming areas. Our methodology is based on the three following steps: VHDL code modeling and analysis, constraints-based stimuli generation and test sequences generation.
Domaines
Electronique
Origine : Fichiers produits par l'(les) auteur(s)
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