Analysis and Compact Modeling of a Vertical Grounded-Base NPN Bipolar Transistor used as ESD Protection in a Smart Power Technology
Résumé
A thorough analysis of the physical mechanisms involved in a Vertical Grounded-Base NPN bipolar transistor (VGBNPN) under ElectroStatic Discharge (ESD) stress is first carried out by using 2D-device simulation, Transmission Line Pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed.
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