J. Larus and C. Kozyrakis, Transactional memory, Communications of the ACM, vol.51, issue.7, pp.80-88, 2008.
DOI : 10.1145/1364782.1364800

M. Herlihy and J. E. Moss, Transactional memory, ACM SIGARCH Computer Architecture News, vol.21, issue.2, pp.289-300, 1993.
DOI : 10.1145/173682.165164

P. Felber, C. Fetzer, and T. , Dynamic performance tuning of word-based software transactional memory, Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming , PPoPP '08, pp.237-246, 2008.
DOI : 10.1145/1345206.1345241
URL : http://doc.rero.ch/record/18074/files/Felber_Pascal_-_Dynamic_Performance_Tuning_of_Word-Based_Software_20100419.pdf

P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir et al., Hybrid transactional memory, ACM SIGPLAN Notices, vol.41, issue.11, pp.336-346, 2006.
DOI : 10.1145/1168918.1168900

M. B. Castro, Improving the Performance of Transactional Memory Applications on Multicores: A Machine Learning-based Approach, 2012.
URL : https://hal.archives-ouvertes.fr/tel-00766983

J. O. Kephart and D. M. Chess, The vision of autonomic computing, Computer, vol.36, issue.1, pp.41-50, 2003.
DOI : 10.1109/MC.2003.1160055

N. Zhou, G. Delaval, B. Robu, É. Rutten, and J. Méhaut, Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory, 2016 IEEE International Conference on Autonomic Computing (ICAC), 2016.
DOI : 10.1109/ICAC.2016.54
URL : https://hal.archives-ouvertes.fr/hal-01309681

N. Zhou, G. Delaval, B. Robu, É. Rutten, and J. Méhaut, Control of autonomic parallelism adaptation on software transactional memory, 2016 International Conference on High Performance Computing & Simulation (HPCS), 2016.
DOI : 10.1109/HPCSim.2016.7568333
URL : https://hal.archives-ouvertes.fr/hal-01309195

G. E. Moore, Cramming More Components Onto Integrated Circuits, Proceedings of the IEEE, pp.82-85, 1998.
DOI : 10.1109/JPROC.1998.658762

H. Esmaeilzadeh, E. Blem, R. St, K. Amant, D. Sankaralingam et al., Dark silicon and the end of multicore scaling, Proceedings of the 38th Annual International Symposium on Computer Architecture, pp.365-376, 2011.

J. L. Hennessy and D. A. Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach, 2006.

L. Mcvoy and C. Staelin, Lmbench: Portable Tools for Performance Analysis, Proceedings of the 1996 Annual Conference on USENIX Annual Technical Conference, ATEC '96, pp.23-23, 1996.

A. Vajda, Programming Many-Core Chips, 2011.
DOI : 10.1007/978-1-4419-9739-5
URL : https://link.springer.com/content/pdf/bfm%3A978-1-4419-9739-5%2F1.pdf

R. Kumar, D. M. Tullsen, N. P. Jouppi, and P. Ranganathan, Heterogeneous chip multiprocessors, Computer, vol.38, issue.11, pp.32-38, 2005.
DOI : 10.1109/MC.2005.379

T. E. Anderson, D. D. Lazowska, and H. M. Levy, The performance implications of thread management alternatives for shared-memory multiprocessors, ACM SIGMETRICS Performance Evaluation Review, vol.17, issue.1, pp.49-60, 1989.
DOI : 10.1145/75372.75378

M. Diener, F. Madruga, E. Rodrigues, M. Alves, J. Schneider et al., Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors, 2010 IEEE 12th International Conference on High Performance Computing and Communications (HPCC), pp.491-496, 2010.
DOI : 10.1109/HPCC.2010.114
URL : http://www.user.tu-berlin.de/komm/paper/2010-Diener-et-al-Thread-Placement-based-on-Memory-Access-Patterns.pdf

A. Agawal and A. Gupta, Memory-reference characteristics of multiprocessor applications under MACH, ACM SIGMETRICS Performance Evaluation Review, vol.16, issue.1, pp.215-225, 1988.
DOI : 10.1145/1007771.55620

R. Thekkath and S. J. Eggers, Impact of sharing-based thread placement on multithreaded architectures, Computer Architecture Proceedings the 21st Annual International Symposium on, pp.176-186, 1994.

J. A. Brown, L. Porter, and D. M. Tullsen, Fast thread migration via cache working set prediction, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, pp.193-204, 2011.
DOI : 10.1109/HPCA.2011.5749728
URL : http://cseweb.ucsd.edu/users/tullsen/HPCA2011brown.pdf

C. Terboven, D. Mey, D. Schmidl, H. Jin, and T. Reichstein, Data and thread affinity in openmp programs, Proceedings of the 2008 workshop on Memory access on future processors a solved problem?, MAW '08, pp.377-384, 2008.
DOI : 10.1145/1366219.1366222

M. B. Greenwald, Non-Blocking Synchronization and System Design, 1999.
DOI : 10.1145/238721.238767
URL : http://www.usenix.org/publications/library/proceedings/osdi96/full_papers/greenwald/greenwald.ps

A. Bahra, Nonblocking algorithms and scalable multicore programming, Communications of the ACM, vol.56, issue.7, pp.50-61, 2013.
DOI : 10.1145/2483852.2483866

M. Herlihy, V. Luchangco, M. Moir, W. N. Scherer, and I. , Software transactional memory for dynamic-sized data structures, Proceedings of the twenty-second annual symposium on Principles of distributed computing , PODC '03, pp.92-101, 2003.
DOI : 10.1145/872035.872048
URL : http://www.distcomp.ethz.ch/lectures/fs10/seminar/paper/johannes-1.pdf

M. Herlihy, Wait-free synchronization, ACM Transactions on Programming Languages and Systems, vol.13, issue.1, pp.124-149, 1991.
DOI : 10.1145/114005.102808

V. J. Marathe and M. L. Scott, A Qualitative Survey of Modern Software Transactional Memory Systems, 2004.

T. Harris, M. Plesko, A. Shinnar, and D. Tarditi, Optimizing memory transactions, ACM SIGPLAN Notices, vol.41, issue.6, pp.14-25, 2006.
DOI : 10.1145/1133255.1133984

D. B. Lomet, Process structuring, synchronization, and recovery using atomic actions, ACM SIGOPS Operating Systems Review, vol.11, issue.2, pp.128-137, 1977.
DOI : 10.1145/390018.808319

J. Gray, Notes on Data Base Operating Systems, " in Operating Systems, An Advanced Course, pp.393-481, 1978.
DOI : 10.1007/3-540-08755-9_9

J. E. Herlihy, Transactional memory: Architectural support for lock-free data structures, tech. rep, 1992.
DOI : 10.1109/isca.1993.698569
URL : http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-895-theory-of-parallel-systems-sma-5509-fall-2003/readings/herlihy_mo93.pdf

E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide et al., Hybrid Transactional Memory with Pessimistic Concurrency Control, International Journal of Parallel Programming, vol.15, issue.6, pp.375-396, 2010.
DOI : 10.1109/TPDS.2004.8

Z. He, X. Yu, B. Hong-]-m, K. Ansari, C. Jarvis et al., Profiling-based adaptive contention management for software transactional memory Profiling transactional memory applications, Parallel Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International Parallel, Distributed and Networkbased Processing 17th Euromicro International Conference on, pp.1204-1215, 2009.
DOI : 10.1109/ipdps.2012.110

D. Rughetti, P. Di-sanzo, B. Ciciani, and F. Quaglia, Machine Learning-Based Self-Adjusting Concurrency in Software Transactional Memory Systems, 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp.278-285, 2012.
DOI : 10.1109/MASCOTS.2012.40

D. Rughetti, P. D. Sanzo, B. Ciciani, and F. Quaglia, Dynamic Feature Selection for Machine-Learning Based Concurrency Regulation in STM, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp.68-75, 2014.
DOI : 10.1109/PDP.2014.24

P. D. Sanzo, F. D. Re, D. Rughetti, B. Ciciani, and F. Quaglia, Regulating Concurrency in Software Transactional Memory: An Effective Model-based Approach, 2013 IEEE 7th International Conference on Self-Adaptive and Self-Organizing Systems, pp.31-40, 2013.
DOI : 10.1109/SASO.2013.35

M. M. Pereira, M. Gaudet, J. N. Amaral, and G. Araujo, Study of hardware transactional memory characteristics and serialization policies on haswell, Parallel Computing, p.2015

E. Koskinen and M. Herlihy, Checkpoints and continuations instead of nested transactions, Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures, SPAA '08, pp.160-168, 2008.
DOI : 10.1145/1378533.1378563
URL : http://www.cs.brown.edu/people/ejk/papers/checkpoints-conf.pdf

N. Diegues and P. Romano, Self-Tuning Intel Transactional Synchronization Extensions, 11th International Conference on Autonomic Computing (ICAC 14), pp.209-219, 2014.

D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco et al., Applications of the adaptive transactional memory test platform, the TRANSACT'08:3rd Workshop on Transactional Computing, 2008.

S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen, Hybrid transactional memory, Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming , PPoPP '06, pp.209-220, 2006.
DOI : 10.1145/1122971.1123003
URL : http://www.cs.princeton.edu/~skumar/papers/ppopp06/ppopp06.pdf

D. Dice, O. Shalev, and N. Shavit, Transactional Locking II, Proceedings of the 20th International Conference on Distributed Computing, pp.194-208, 2006.
DOI : 10.1007/11864219_14

A. Dragojevi´cdragojevi´c, R. Guerraoui, and M. Kapalka, Stretching transactional memory, ACM SIGPLAN Notices, vol.44, issue.6, pp.155-165, 2009.
DOI : 10.1145/1543135.1542494

V. J. Marathe, M. F. Spear, C. Heriot, A. Acharya, D. Eisenstat et al., Lowering the Overhead of Nonblocking Software Transactional Memory, 2006.

K. Fraser and T. Harris, Concurrent programming without locks, ACM Transactions on Computer Systems, vol.25, issue.2, 2007.
DOI : 10.1145/1233307.1233309

M. Ansari, C. Kotselidis, I. Watson, C. Kirkham, M. Lujã et al., Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory, Algorithms and Architectures for Parallel Processing, pp.196-207, 2008.
DOI : 10.1007/978-3-540-69501-1_21
URL : http://www.cs.man.ac.uk/apt/projects/TM/pdfs/ica3pp08-ansari.pdf

G. Kestor, V. Karakostas, O. S. Unsal, A. Cristal, I. Hur et al., RMS- TM: a comprehensive benchmark suite for transactional memory systems, pp.335-346, 2011.

R. Guerraoui, M. Kapalka, and J. Vitek, STMBench7, ACM SIGOPS Operating Systems Review, vol.41, issue.3, pp.315-324, 2007.
DOI : 10.1145/1272998.1273029

F. Zyulkyarov, A. Cristal, S. Cvijic, E. Ayguade, M. Valero et al., WormBench, Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture, MEDEA '08, pp.61-68, 2008.
DOI : 10.1145/1509084.1509093

C. , C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun, STAMP: Stanford transactional applications for multi-processing, IEEE International Symposium on Workload Characterization (IISWC), 2008.

W. Ruan, Y. Liu, and M. Spear, STAMP need not be considered harmful, 9th ACM SIGPLAN Workshop on Transactional Computing, 2014.

C. Y. Lee, An Algorithm for Path Connections and Its Applications, IEEE Transactions on Electronic Computers, vol.10, issue.3, pp.346-365, 1961.
DOI : 10.1109/TEC.1961.5219222

J. Ruppert, A Delaunay Refinement Algorithm for Quality 2-Dimensional Mesh Generation, Journal of Algorithms, vol.18, issue.3, pp.548-585, 1995.
DOI : 10.1006/jagm.1995.1021

M. C. Huebscher and J. A. Mccann, A survey of autonomic computing???degrees, models, and applications, ACM Computing Surveys, vol.40, issue.3, pp.1-728, 2008.
DOI : 10.1145/1380584.1380585

Y. Sun, J. Lifflander, and L. V. Kalé, PICS, Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, ROSS '14, 2014.
DOI : 10.1145/2612262.2612266

I. J. Dooley, Intelligent Runtime Tuning of Parallel Applications with Control Points

E. Rutten, N. Marchand, and D. Simon, Feedback Control as MAPE-K loop in Autonomic Computing, Software Engineering for Self-Adaptive Systems, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01285014

M. Litoiu, M. Shaw, G. Tamura, N. M. Villegas, H. Müller et al., What Can Control Theory Teach Us About Assurances in Self- Adaptive Software Systems?, Software Engineering for Self-Adaptive Systems 3: Assurances (R. de Lemos, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01281063

H. Müller, M. Pezzè, and M. Shaw, Visibility of control in adaptive systems, Proceedings of the 2nd international workshop on Ultra-large-scale software-intensive systems , ULSSIS '08, pp.23-26, 2008.
DOI : 10.1145/1370700.1370707

Y. Brun, G. Marzo-serugendo, C. Gacek, H. Giese, H. Kienle et al., Software engineering for self-adaptive systems , " ch. Engineering Self-Adaptive Systems Through Feedback Loops, pp.48-70, 2009.

W. L. Brogan, Modern Control Theory Upper Saddle River, 1991.

C. G. Cassandras and S. Lafortune, Introduction to Discrete Event Systems, 2001.

A. S. Dhodapkar and J. E. Smith, Comparing program phase detection techniques, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), p.217, 2003.
DOI : 10.1109/MICRO.2003.1253197

A. Silberschatz, WCS)Operating System Concepts 7th Edition Flex Format, 2005.

M. Ansari, C. Kotselidis, K. Jarvis, M. Luján, C. Kirkham et al., Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate, Proceedings of the 14th International Euro-Par Conference on Parallel Processing, Euro-Par '08, pp.719-728, 2008.
DOI : 10.1007/978-3-540-85451-7_77

M. Ansari, C. Kotselidis, K. Jarvis, M. Luján, C. Kirkham et al., Adaptive concurrency control for transactional memory, MULTIPROG '08: First Workshop on Programmability Issues for Multi-Core Computers, 2008.
DOI : 10.1007/s11227-014-1138-5

K. Ravichandran, S. Pande, D. Didona, P. Felber, D. Harmanci et al., F2C2-STM: Flux-based feedback-driven concurrency control for STMs Identifying the optimal level of parallelism in transactional memory applications, Parallel and Distributed Processing Symposium, [77], pp.233-247, 2013.

J. Wamhoff, C. Fetzer, P. Felber, E. Rivière, and G. Muller, Fastlane: Improving performance of software transactional memory for low thread counts, Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming, PPoPP '13, pp.113-122, 2013.

D. Christie, J. Chung, S. Diestelhorst, M. Hohmuth, M. Pohlack et al., Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack, Proceedings of the 5th European conference on Computer systems, EuroSys '10, pp.27-40, 2010.
DOI : 10.1145/1755913.1755918

A. Dragojevi´cdragojevi´c, P. Felber, V. Gramoli, and R. Guerraoui, Why STM can be more than a research toy, Communications of the ACM, vol.54, issue.4, pp.70-77, 2011.
DOI : 10.1145/1924421.1924440

E. Jeannot and G. Mercier, Near-Optimal Placement of MPI Processes on Hierarchical NUMA Architectures, pp.199-210, 2010.
DOI : 10.1145/1654059.1654087
URL : https://hal.archives-ouvertes.fr/inria-00544346

S. Hong, S. Narayanan, M. Kandemir, and O. Ozturk, Process variation aware thread mapping for Chip Multiprocessors, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.821-826, 2009.
DOI : 10.1109/DATE.2009.5090776
URL : http://repository.bilkent.edu.tr/bitstream/11693/28728/1/Process%20variation%20aware%20thread%20mapping%20for%20chip%20multiprocessors.pdf

G. Tournavitis, Z. Wang, B. Franke, and M. F. O-'boyle, Towards a holistic approach to auto-parallelization, ACM SIGPLAN Notices, vol.44, issue.6, pp.177-187, 2009.
DOI : 10.1145/1543135.1542496

W. Gropp, E. Lusk, and A. Skjellum, Using MPI: Portable Parallel Programming with the Message-passing Interface, 1994.

L. Dagum and R. Menon, OpenMP: an industry standard API for shared-memory programming, IEEE Computational Science and Engineering, vol.5, issue.1, pp.46-55, 1998.
DOI : 10.1109/99.660313

M. Castro, L. F. Goes, and J. Mehaut, Adaptive thread mapping strategies for transactional memory applications, Journal of Parallel and Distributed Computing, vol.74, issue.9, pp.2845-2859, 2014.
DOI : 10.1016/j.jpdc.2014.05.008
URL : https://hal.archives-ouvertes.fr/hal-01127722

M. Castro, L. F. Goes, C. P. Ribeiro, M. Cole, M. Cintra et al., A machine learning-based approach for thread mapping on transactional memory applications, 2011 18th International Conference on High Performance Computing, pp.1-10, 2011.
DOI : 10.1109/HiPC.2011.6152736
URL : https://hal.archives-ouvertes.fr/hal-00788791

Z. Wang and M. F. O-'boyle, Mapping parallelism to multi-cores, ACM SIGPLAN Notices, vol.44, issue.4, pp.75-84, 2009.
DOI : 10.1145/1594835.1504189

J. Corbalán, X. Martorell, and J. Labarta, Performance-driven processor allocation, Proceedings of the 4th Conference on Symposium on Operating System Design & Implementation USENIX Association, 2000.
DOI : 10.1109/TPDS.2005.85

K. H. Ang, G. Chong, and Y. Li, PID control system analysis, design, and technology, IEEE Transactions on Control Systems Technology, vol.13, pp.559-576, 2005.

G. Delaval, N. De-palma, S. M. Gueye, H. Marchand, and É. Rutten, Discrete Control of Computing Systems Administration: A Programming Language Supported Approach, pp.117-124, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00863276

G. Delaval, H. Marchand, and E. Rutten, Contracts for Modular Discrete Controller Synthesis, ACM International Conference on Languages, Compilers
DOI : 10.1145/1755951.1755898
URL : https://hal.archives-ouvertes.fr/inria-00476910