Skip to Main content Skip to Navigation
New interface
Reports (Research report)

Specification and Verification of the PowerScale Bus Arbitration Protocol:An Industrial Experiment with LOTOS

Abstract : This paper presents the results of an industrial case-study concerning the use of formal methods for the validation of hardware design. The case-study focuses on PowerScale, a multiprocessor architecture based on PowerPC micro-processors and used in Bull's Escala series of servers and workstations. The specification language LOTOS (ISO International Standard 8807) was used to describe formally the main components of this architecture (processors, memory controller and bus arbiter). Four correctness properties were identified, which express the essential requirements for a proper functioning of the arbitration algorithm, and formalized in terms of bisimulation relations (modulo abstractions) between finite labelled transition systems. Using the compositional and on-the-fly model-checking techniques implemented in the CADP (CAESAR/ALDEBARAN) toolbox, the correctness of the arbitration algorithm was established automatically in a few minutes.
Document type :
Reports (Research report)
Complete list of metadata

https://hal.inria.fr/inria-00073740
Contributor : Rapport De Recherche Inria Connect in order to contact the contributor
Submitted on : Wednesday, May 24, 2006 - 1:39:24 PM
Last modification on : Thursday, October 27, 2022 - 4:02:54 AM
Long-term archiving on: : Sunday, April 4, 2010 - 11:56:42 PM

Identifiers

  • HAL Id : inria-00073740, version 1

Citation

Ghassan Chehaibar, Hubert Garavel, Laurent Mounier, Nadia Tawbi, Ferruccio Zulian. Specification and Verification of the PowerScale Bus Arbitration Protocol:An Industrial Experiment with LOTOS. [Research Report] RR-2958, INRIA. 1996. ⟨inria-00073740⟩

Share

Metrics

Record views

148

Files downloads

445