A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM

Y. Zhou (1) , H. Cai (1) , M. Zhang (1) , L.A.B. Naviner (2, 3) , J. Yang (1)

1 Southeast University
2 SSH - Secure and Safe Hardware
3 COMELEC - Département Communications & Electronique

This paper proposes a novel methodology to design high reliable STT-MRAM, with self-activated built-in-self-test (BIST) against aging/temperature-induced degradation. During sensing operation, tunneling magnetoresistance (TMR) is monitored, and real-time BIST is activated prior to permanent damage in Magnetic tunnel junction (MTJ) stack. To evaluate the feasibility of the test scheme, the proposed technique was involved in MRAM array implementation using 28-nm CMOS and 40-nm MTJ. HSPICE MOS Reliability Analysis (MOSRA) is used to evaluate the amount of electrical stress to the actual device aging degradation. Compared with previous periodical BIST method, the proposed self-triggered BIST saves ~31.1% cumulative power consumption over 12 years. And the proposed technique can improve reliability in the wear-out failure period.

Domaines: Sciences de l'ingénieur [physics]; Micro et nanotechnologies/Microélectronique; Electronique

Y. Zhou, H. Cai, M. Zhang, L.A.B. Naviner, J. Yang. A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM. Microelectronics Reliability, 2020, 114, pp.113735. ⟨10.1016/j.microrel.2020.113735⟩. ⟨hal-03493058⟩