Introducing 32 nm technology in Microwind35

Etienne Sicard (1) , Syed Mahfuzul Aziz (2)

1 INSA Toulouse - Institut National des Sciences Appliquées - Toulouse
2 University of South Australia [Adelaide]

This paper describes the improvements related to the CMOS 32 nm technology and the implementation of this technology in Microwind35. The main novelties related to the 32 nm technology such as the high-k gate oxide, 3 rd generation channel strain, metal-gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6-transistor RAM memory layout are also analyzed.

Domaines: Micro et nanotechnologies/Microélectronique

Etienne Sicard, Syed Mahfuzul Aziz. Introducing 32 nm technology in Microwind35. 2011. ⟨hal-03324299⟩