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Introducing 32 nm technology in Microwind35

Abstract : This paper describes the improvements related to the CMOS 32 nm technology and the implementation of this technology in Microwind35. The main novelties related to the 32 nm technology such as the high-k gate oxide, 3 rd generation channel strain, metal-gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6-transistor RAM memory layout are also analyzed.
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https://hal.archives-ouvertes.fr/hal-03324299
Contributor : Etienne Sicard Connect in order to contact the contributor
Submitted on : Monday, August 23, 2021 - 2:49:42 PM
Last modification on : Tuesday, October 19, 2021 - 11:17:37 PM
Long-term archiving on: : Wednesday, November 24, 2021 - 6:37:09 PM

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  • HAL Id : hal-03324299, version 1

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Etienne Sicard, Syed Aziz. Introducing 32 nm technology in Microwind35. 2011. ⟨hal-03324299⟩

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