A Multi-Core Fault Tolerance Approach Based on Coded-Processing

Lukas Osinski , Ralph Mader (1) , Jens Harnisch , Jürgen Mottok

1 Continental Automotive Germany AG [Regensburg]

Development trends for computing platforms moved from increasing the frequency of a single processor to increasing the parallelism with multiple cores on the same die. Multiple cores have strong potential to support cost-efficient fault tolerance due to their inherent spatial redundancy. This work makes a step towards software-only fault tolerance in the presence of permanent and transient hardware faults. Our approach utilizes software-based spatial triple modular redundancy and coded processing on a shared memory multi-core controller. We evaluate our approach on an Infineon AURIX TriBoard TC277 and provide experimental evidence for error resistance by fault injection campaigns with an iSystem iC5000 On-chip Analyzer.

Mots clés: Index Terms-Fault Detection; Triple Modular Redundancy (TMR); Fault Tolerance; Multi-Core; Coded Processing; Shared Memory; Spatial Redundancy

Domaines: Informatique et langage [cs.CL]

Lukas Osinski, Ralph Mader, Jens Harnisch, Jürgen Mottok. A Multi-Core Fault Tolerance Approach Based on Coded-Processing. ERTS 2018, Jan 2018, Toulouse, France. ⟨hal-02156233⟩