B. M. Maggs, L. R. Matheson, and R. E. Tarjan, Models of parallel computation: a survey and synthesis, Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, pp.61-70, 1995.
DOI : 10.1109/HICSS.1995.375476

T. Grandpierre and Y. Sorel, From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings., pp.123-132, 2003.
DOI : 10.1109/MEMCOD.2003.1210097

A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski et al., Electronic System-Level Synthesis Methodologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.10, pp.1517-1530, 2009.
DOI : 10.1109/TCAD.2009.2026356

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.160.5391

M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot et al., Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 2016.
DOI : 10.1109/SiPS.2016.29

URL : https://hal.archives-ouvertes.fr/hal-01390508

F. Baccelli, G. Cohen, G. J. Olsder, and J. Quadrat, Synchronization and linearity: an algebra for discrete event systems, 1992.

N. Bambha, V. Kianzad, M. Khandelia, and S. S. Bhattacharyya, Intermediate representations for design automation of multiprocessor DSP systems, Design Automation for Embedded Systems, vol.7, issue.4, pp.307-323, 2002.
DOI : 10.1023/A:1020307222052

B. Kienhuis, E. Deprettere, K. Vissers, P. Van, and . Wolf, An approach for quantitative analysis of application-specific dataflow architectures, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp.338-349, 1997.
DOI : 10.1109/ASAP.1997.606839

J. Eker, J. Janneck, E. Lee, J. Liu, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, pp.127-144, 2003.
DOI : 10.1109/JPROC.2002.805829

M. Pelcat, S. Aridhi, J. Piat, and J. Nezan, Physical Layer Multi- Core Prototyping: A Dataflow-Based Approach for LTE eNodeB, 2012.
DOI : 10.1007/978-1-4471-4210-2

URL : https://hal.archives-ouvertes.fr/hal-00739957

E. A. Lee and D. G. Messerschmitt, Synchronous data flow, Proceedings of the IEEE, 1987.
DOI : 10.1109/PROC.1987.13876

E. A. Lee and T. M. Parks, Dataflow process networks, Proceedings of the IEEE, 1995.
DOI : 10.1109/5.381846

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.21.2539

W. Plishker, N. Sane, M. Kiemb, and S. S. Bhattacharyya, Heterogeneous design in functional DIF, Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, pp.157-166, 2008.

W. Plishker, N. Sane, M. Kiemb, K. Anand, and S. S. Bhattacharyya, Functional DIF for Rapid Prototyping, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, pp.17-23, 2008.
DOI : 10.1109/RSP.2008.32

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.7185

L. Valiant, A bridging model for parallel computation, Communications of the ACM, vol.33, issue.8, pp.103-111, 1990.
DOI : 10.1145/79173.79181

G. E. Box and N. R. Draper, Empirical model-building and response surfaces, 1987.

B. Kienhuis, E. F. Deprettere, P. Van-der, K. Wolf, and . Vissers, A methodology to design programmable embedded systems, " in Embedded processor design challenges, pp.18-37, 2002.

J. Ceng, W. Sheng, J. Castrillon, A. Stulova, R. Leupers et al., A high-level virtual platform for early MPSoC software development, Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, CODES+ISSS '09, pp.11-20, 2009.
DOI : 10.1145/1629435.1629438

P. H. Feiler, D. P. Gluch, and J. J. Hudak, The architecture analysis & design language (AADL): An introduction, 2006.

J. , C. Mazo, and R. Leupers, Programming Heterogeneous MPSoCs

V. Kianzad and S. S. Bhattacharyya, CHARMED: A multi-objective cosynthesis framework for multi-mode embedded systems, Application- Specific Systems, Architectures and Processors Proceedings. 15th IEEE International Conference on, pp.28-40, 2004.

T. Grandpierre and Y. Sorel, Un nouveau modèle générique d'architecture hétérogène pour la méthodologie AAA, Actes JFAAA'02, 2002.

E. Raffin, C. Wolinski, F. Charot, K. Kuchcinski, S. Guyetant et al., Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture, Design and Architectures for Signal and Image Processing 2010 Conference on, pp.168-175, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00663458

M. Pelcat, J. Nezan, J. Piat, J. Croizer, and S. Aridhi, A systemlevel architecture model for rapid prototyping of heterogeneous multicore embedded systems, Proceedings of DASIP conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00429397

A. Donlin, Transaction level modeling, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.75-80, 2004.
DOI : 10.1145/1016720.1016742

R. Aster, B. Borchers, and C. Thurber, Parameter estimation and inverse problems, 2011.

M. Pelcat, K. Desnos, J. Heulot, C. Guy, J. Nezan et al., Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.36-40, 2014.
DOI : 10.1109/EDERC.2014.6924354

URL : https://hal.archives-ouvertes.fr/hal-01059313

K. Desnos, M. Pelcat, J. Nezan, S. S. Bhattacharyya, and S. Aridhi, PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013.
DOI : 10.1109/SAMOS.2013.6621104

URL : https://hal.archives-ouvertes.fr/hal-00877492

A. Mercat, J. Nezan, D. Menard, and J. Zhang, Implementation of a Stereo Matching algorithm onto a Manycore Embedded System, 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1296-1299, 2014.
DOI : 10.1109/ISCAS.2014.6865380

K. Desnos and J. Zhang, PREESM project -stereo matching svn://svn .code.sf, 2013.

N. K. Bambha and S. S. Bhattacharyya, A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct, Proceedings 13th International Symposium on System Synthesis, pp.91-97, 2000.
DOI : 10.1109/ISSS.2000.874034