S. Tanimoto and K. Matsui, High Junction Temperature and Low Parasitic Inductance Power Module Technology for Compact Power Conversion Systems, IEEE Transactions on Electron Devices, vol.62, issue.2, pp.258-269, 2015.
DOI : 10.1109/TED.2014.2359978

S. Li and L. M. Tolbert, Fei Wang; Fang Zheng PengStray Inductance Reduction of Commutation Loop in the P-cell and N-cell- Based IGBT Phase Leg Module, IEEE Transactions on, vol.29, issue.7, pp.3616-3624, 2014.

B. Yi, Z. Lin, and X. Chen, Snapback-free reverse-conducting IGBT with low turnoff loss, Electronics Letters, vol.50, issue.9, pp.703-705, 2014.
DOI : 10.1049/el.2014.0169

U. Vemulapati, N. Kaminski, D. Silber, L. Storasta, and M. Rahimo, Reverse conducting???IGBTs initial snapback phenomenon and its analytical modelling, IET Circuits, Devices & Systems, vol.8, issue.3, pp.168-175, 2014.
DOI : 10.1049/iet-cds.2013.0222

A. Khadiry, A. Bourennane, F. Richardeau, and E. Imberrnon, New Monolithic Multi-poles Converter Device for Medium Power Applications, European Power Electronics Conference and Application, pp.26-28

D. W. Green and E. Shankar-narayanan, Fully Isolated High Side and Low Side LIGBTs in Junction Isolation Technology", Power Semiconductor Devices and IC's, ISPSD 2006, IEEE International Symposium on, pp.1-4, 2006.

L. Benaissa, A vertical power device conductive assembly at wafer level using direct bonding technology, 2012 24th International Symposium on Power Semiconductor Devices and ICs, pp.77-80, 2012.
DOI : 10.1109/ISPSD.2012.6229027
URL : https://hal.archives-ouvertes.fr/hal-00820244

E. Imbernon, Flexible technological process for functional integration, 2001 International Semiconductor Conference. CAS 2001 Proceedings (Cat. No.01TH8547), pp.65-68
DOI : 10.1109/SMICND.2001.967506

A. Khadiry, A. Bourennane, and F. Richardeau, Multiphase Power Converter Integration in Si: Dual-Chip and Ultimate Monolithic Integrations, IEEE Transactions on Electron Devices, pp.1977-1983, 2016.
DOI : 10.1109/TED.2016.2537212

J. Sanchez, Realization of vertical P/sup +/ walls through-wafer for bi-directional current and voltage power integrated devices, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings., pp.195-198, 2003.
DOI : 10.1109/ISPSD.2003.1225262

O. Causse, P. Austin, J. L. Sanchez, G. Bonnet, and E. Scheid, Achievement of a new peripheral planar structure supporting a symmetrical blocking voltage, 9th European Conference on Power Electronics and Applications (EPE'2001), pp.27-29

T. Rossignol, F. Senghor, D. Risaletto, J. Blaquière, F. Richardeau et al., Switching optimization of WBG power devices on inverter leg " dv/dt ? switching energy " trade off and comparison using directly the gate resistance or an additional feedback gate-drain capacitor, pp.16-18