B. Murari, F. Bertotti, and G. Vignola, Smart Power ICs, 2002.
DOI : 10.1007/978-3-642-61395-1

M. Schenkel, P. Pfaffli, S. Mettler, and W. Reiner, Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection, 30th European Solid-State Device Research Conference, pp.600-603, 2010.
DOI : 10.1109/ESSDERC.2000.194849

M. Schenkel, Substrate Current Effects in Smart Power ICs, p.14925, 2003.

F. Lo-conte, ;. Sallese, and M. , A Circuit-Level Substrate Current Model for Smart Power ICs, IEEE Transactions on, vol.25, issue.9, pp.2433-2439, 2010.

Y. Moursy, AUTOMICS: A Novel Approach for Substrate Modeling, 18th IEEE European Test Symposium, 2013.
URL : https://hal.archives-ouvertes.fr/hal-01078755

P. Buccella, C. Stefanucci, H. Zou, Y. Moursy, R. Iskander et al., Methodology for 3-D Substrate Network Extraction for Spice Simulation of Parasitic Currents in Smart Power ICs Computer- Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2015.

C. Stefanucci, P. Buccella, M. Kayal, and J. Salles, Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs, Solid-State Electronics, vol.105, pp.21-29, 2015.
DOI : 10.1016/j.sse.2014.11.016

C. Stefanucci, P. Buccella, M. Kayal, and J. Salles, Impact of enhanced contact doping on minority carriers diffusion currents, 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp.1-4
DOI : 10.1109/PRIME.2014.6872738

H. Zou, Y. Moursy, R. Iskander, J. Chaput, and M. Louërat, A novel CAD Framework for Substrate Modeling, Microelectronics and Electronics (PRIME), 2014 10 th Conference on Ph.D, pp.1-4
URL : https://hal.archives-ouvertes.fr/hal-01078767

F. Lo-conte, J. Sallese, and M. , Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage Hbridge at High Temperature, IEEE Transactions on, vol.26, issue.10, pp.2788-2793, 2011.

H. Zou, Y. Moursy, R. Iskander, C. Stefanucci, P. Buccella et al., Substrate noise modeling with dedicated CAD framework for smart power ICs, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1554-1557, 2015.
DOI : 10.1109/ISCAS.2015.7168943

URL : https://hal.archives-ouvertes.fr/hal-01230110

P. Buccella, C. Stefanucci, J. Salles, and M. Kayal, Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs, IEEE Transactions on Power Electronics, vol.31, issue.9, pp.6586-6595, 2015.
DOI : 10.1109/TPEL.2015.2502759

Y. Moursy, H. Zou, R. Iskander, P. Tisserand, D. Ton et al., Towards Automotic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.265-268, 2016.

Y. Moursy-;-h, R. Zou, R. Khalil, . Iskander-;-p, . M. Tisserand-;-d et al., Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications, IEEE Transactions on Power Electronics, pp.1-1
DOI : 10.1109/TPEL.2016.2604818

H. Openaccess, Y. Zou, R. Moursy, J. Iskander, M. Chaput et al., An Adaptive Mesh Refinement Strategy for Substrate Modeling, Circuit and Systems (ISCAS), IEEE International Symposium on, 2016.

V. Tomasevic, A. Boyer, and S. B. Dhia, Bandgap failure study due to parasitic bipolar substrate coupling in Smart Power mixed ICs, 2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), pp.34-38, 2015.
DOI : 10.1109/EMCCompo.2015.7358326

URL : https://hal.archives-ouvertes.fr/hal-01225358

H. Zou-received-his and B. Sc, degree in Electrical Engineering in 2011 and his M.Sc. degree in Electrical Engineering and Computer Science in 2013 from Université Pierre et Marie Curie (UPMC) Since 2013, he is pursuing his Ph.D. degree at the Laboratoire d'Informatique de Paris 6 (LIP6) at the same university, His research interests are substrate parasitic modeling for smart power ICs and Electronics Design Automation developments

E. Seebacher-earned and A. M. Sc, in physics at Graz University of Technology in 1993 From 1994- 1998 he has been working in the R&D department of austriamicrosystems, on compact modeling of CMOS, BiCMOS and HV CMOS processes. Since 1999 he is the section manager of a group responsible for compact modeling, process characterization, physical verification, and DFM. His scientific interests are compact modeling of MOS, bipolar transistors and passive elements mixed-mode circuits and specialized electro-optical system-on-chip solutions

. Jean-paul, UPMC) in 1993. He is now Research Engineer at the Computer Science Laboratory (LIP6)