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Conference papers
Substrate noise modeling with dedicated CAD framework for smart power ICs
Abstract : In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation into the substrate is not considered in most of existing circuit simulators. In this paper, a novel computer-aided design tool for substrate parasitic extraction is proposed. A simple circuit with an injecting and a collecting N-wells over a P-substrate is studied. With the distance between the wells varying, the lateral bipolar effect is illustrated. The spectre simulation results of extracted substrate equivalent circuit are compared to a TCAD simulation results. The comparison shows an acceptable relevant error. However, the simulation time was reduced by approximately 1400 times with respect to the TCAD.
Cited literature [8 references]
https://hal.sorbonne-universite.fr/hal-01230110
Contributor : Hao Zou <>
Submitted on : Tuesday, November 17, 2015 - 5:54:54 PM
Last modification on : Thursday, March 21, 2019 - 2:39:48 PM
Document(s) archivé(s) le : Friday, April 28, 2017 - 9:40:31 PM
Contributor : Hao Zou <>
Submitted on : Tuesday, November 17, 2015 - 5:54:54 PM
Last modification on : Thursday, March 21, 2019 - 2:39:48 PM
Document(s) archivé(s) le : Friday, April 28, 2017 - 9:40:31 PM
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PID3557751.pdf
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