M. Bruce, L. R. Maggs, R. E. Matheson, and . Tarjan, Models of parallel computation: A survey and synthesis, System Sciences Proceedings of the Twenty-Eighth Hawaii International Conference on, pp.61-70, 1995.

T. Grandpierre and Y. Sorel, From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings., pp.123-132, 2003.
DOI : 10.1109/MEMCOD.2003.1210097

S. Shuvra, . Bhattacharyya, F. Ed, R. Deprettere, J. Leupers et al., Handbook of signal processing systems, 2013.

J. Castrillon, M. , and R. Leupers, Programming Heterogeneous MPSoCs
DOI : 10.1007/978-3-319-00675-8

. Xilinx, UltraScale Architecture and Product Overview, 2015.

F. Baccelli, G. Cohen, G. J. Olsder, and J. Quadrat, Synchronization and linearity: an algebra for discrete event systems, 1992.

N. Bambha, V. Kianzad, M. Khandelia, and S. S. Bhattacharyya, Intermediate representations for design automation of multiprocessor DSP systems, Design Automation for Embedded Systems, vol.7, issue.4, pp.307-323, 2002.
DOI : 10.1023/A:1020307222052

B. Kienhuis, E. Deprettere, K. Vissers, P. Van, and . Wolf, An approach for quantitative analysis of application-specific dataflow architectures, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp.338-349, 1997.
DOI : 10.1109/ASAP.1997.606839

J. Eker, W. Jörn, E. Janneck, J. Lee, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, pp.127-144, 2003.
DOI : 10.1109/JPROC.2002.805829

M. Pelcat, S. Aridhi, J. Piat, and J. Nezan, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB, 2012.
DOI : 10.1007/978-1-4471-4210-2
URL : https://hal.archives-ouvertes.fr/hal-00739957

H. Yviquel, From dataflow-based video coding tools to dedicated embedded multi-core platforms, 2013.
URL : https://hal.archives-ouvertes.fr/tel-00939346

A. Edward, . Lee, G. David, and . Messerschmitt, Synchronous data flow, Proceedings of the IEEE, 1987.

A. Edward, T. M. Lee, and . Parks, Dataflow process networks, Proceedings of the IEEE, vol.83, issue.5, 1995.

W. Plishker, N. Sane, M. Kiemb, K. Anand, and S. S. Bhattacharyya, Functional DIF for Rapid Prototyping, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, pp.17-23, 2008.
DOI : 10.1109/RSP.2008.32
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.7185

W. Plishker, N. Sane, M. Kiemb, and S. S. Bhattacharyya, Heterogeneous design in functional DIF, Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, pp.157-166, 2008.

G. Bilsen, M. Engels, R. Lauwereins, and J. A. Peperstraete, Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996.
DOI : 10.1109/78.485935

S. S. Bhattacharyya, E. Deprettere, R. Leupers, and J. Takala, Handbook of Signal Processing Systems, Print, pp.978-979, 2013.

S. S. Bhattacharyya, R. Leupers, and P. Marwedel, Software synthesis and code generation for DSP, IEEE Transactions on Circuits and Systems ? II: Analog and Digital Signal Processing, pp.849-875, 2000.

S. Lin, L. Wang, A. Vosoughi, J. R. Cavallaro, M. Juntti et al., Parameterized Sets of Dataflow Modes And Their Application to Implementation of Cognitive Radio Systems, Journal of Signal Processing Systems, vol.75, issue.9, pp.3-18, 2015.
DOI : 10.1007/s11265-014-0938-4

G. Leslie and . Valiant, A bridging model for parallel computation, Communications of the ACM, vol.33, issue.8, pp.103-111, 1990.

E. George, N. R. Box, and . Draper, Empirical model-building and response surfaces, 1987.

F. Bellard, QEMU, a Fast and Portable Dynamic Translator, USENIX Annual Technical Conference, FREENIX Track, pp.41-46, 2005.

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi et al., The gem5 simulator, Somayeh Sardashti, and others, pp.1-7, 2011.
DOI : 10.1145/2024716.2024718

O. M. Group, UML profile for MARTE: Modeling and analysis of real-time embedded systems, version 1

H. Peter, D. P. Feiler, J. J. Gluch, and . Hudak, The architecture analysis & design language (AADL): An introduction, 2006.

M. Gondo, F. Arakawa, and M. Edahiro, Establishing a standard interface between multi-manycore and software tools-SHIM, " in COOL Chips XVII, pp.1-3, 2014.

J. Ceng, W. Sheng, J. Castrillon, A. Stulova, R. Leupers et al., A high-level virtual platform for early MPSoC software development, Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, CODES+ISSS '09, pp.11-20, 2009.
DOI : 10.1145/1629435.1629438

V. Kianzad and S. S. Bhattacharyya, CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004., pp.28-40, 2004.
DOI : 10.1109/ASAP.2004.1342456

Y. Thierry-grandpierre, . Sorel, and O. Action, Un nouveau modèle générique d'architecture hétérogène pour la méthodologie AAA Actes des Journées Francophones sur l'Adéquation Algorithme Architecture, p.2, 2002.

C. Erwan-raffin, F. Wolinski, K. Charot, S. Kuchcinski, S. Guyetant et al., Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture, Design and Architectures for Signal and Image Processing 2010 Conference on, pp.168-175, 2010.

M. Pelcat, J. Francois-nezan, J. Piat, J. Croizer, and S. Aridhi, A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems, Proceedings of DASIP conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00429397

A. Donlin, Transaction level modeling, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.75-80, 2004.
DOI : 10.1145/1016720.1016742

T. Grandpierre, Modélisation d'architecturesparalì eles hétérogènes pour la génération automatique d'exécutifs distribués temps réel optimisés, 2000.

E. Bezati, R. Thavot, G. Roquier, and M. Mattavelli, High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms Journal of real-time image processing, pp.251-262, 2014.

M. Pelcat, K. Desnos, J. Heulot, C. Guy, J. Nezan et al., Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming, 2014 6th European Embedded Design in Education and Research Conference (EDERC), pp.36-40, 2014.
DOI : 10.1109/EDERC.2014.6924354
URL : https://hal.archives-ouvertes.fr/hal-01059313