EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

Sparsh Mittal (1) , Jeffrey S. Vetter (1)

1 ORNL - Oak Ridge National Laboratory [Oak Ridge]

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (re-sistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to in-crease cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

Mots clés: Non-volatile memory; ReRAM; wear-leveling; intra-set write variation; cache lifetime; write endurance

Domaines: Architectures Matérielles [cs.AR]

Sparsh Mittal, Jeffrey S. Vetter. EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches. 2nd USENIX Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW), Oct 2014, Broomfield, CO, United States. ⟨hal-01104645⟩