W. Huang and E. Mccluskey, Column-based precompiled configuration technique for FPGA fault tolerance, IEEE Field Programmable Custom Computing Machines Symp, 2001.

A. Doumar, S. Kaneko, and H. Ito, Defect and fault tolerance FPGAs by shifting the configuration data, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), pp.377-385, 1999.
DOI : 10.1109/DFTVS.1999.802905

V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep- Submicron FPGAs, 1999.
DOI : 10.1007/978-1-4615-5145-4

. Altera, FPGA -field-programmable gate array

Z. Marrakchi, H. Mrabet, and H. Mehrez, Optimized local interconnect for cluster-based Mesh FPGA architecture, 2008 International Conference on Microelectronics, pp.15-18, 2008.
DOI : 10.1109/ICM.2008.5393494

D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault et al., The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.14-20, 2005.
DOI : 10.1145/1046192.1046195

W. Feng and S. Kaptanoglu, Designing efficient input interconnect blocks for LUT clusters using counting and entropy

Z. Marrakchi, H. Mrabet, and H. Mehrez, Programmable gate array, switch box and logic unit for such an array, 2010.

A. B. Dhia, L. Naviner, and P. Matherat, Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS), 2012.
DOI : 10.1109/IOLTS.2012.6313837
URL : https://hal.archives-ouvertes.fr/hal-01062799

A. Dhia, L. Naviner, and P. Matherat, Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs, 2013 14th Latin American Test Workshop, LATW, 2013.
DOI : 10.1109/LATW.2013.6562661
URL : https://hal.archives-ouvertes.fr/hal-01062112

T. Ban, L. De-barros, and . Naviner, A simple fault-tolerant digital voter circuit in TMR nanoarchitectures, Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010.
DOI : 10.1109/NEWCAS.2010.5603933
URL : https://hal.archives-ouvertes.fr/hal-00637639

A. Yu and G. Lemieux, Defect-tolerant fpga switch block and connection block with fine-grain redundancy for yield enhancement, International Conference on Field Programmable Logic and Applications, 2005., 2005.
DOI : 10.1109/FPL.2005.1515731

F. Monteiro, S. Piestrak, H. Jaber, and A. Dandache, Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), pp.199-200, 2007.
DOI : 10.1109/IOLTS.2007.32

L. Wang, C. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon), 2006.