J. L. Ayala, A. Sridhar, V. Pangracious, D. Atienza, and Y. Leblebici, Through Silicon Via-Based Grid for Thermal Control in 3D Chips, NanoNet Springer, pp.90-98, 2009.

V. Betrz, A. Marquardt, and J. Rose, A New Packing Placement and Routing Tool for FPGA Research. Inter' Workshop on FPGA, pp.213-222, 1997.

V. Betz and J. Rose, Circuit design, transistor sizing and wire layout of FPGA interconnect, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), 1999.
DOI : 10.1109/CICC.1999.777267

I. Kuon, A. Egier, and J. Rose, Design, layout and verification of an FPGA using automated tools, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.215-226, 2005.
DOI : 10.1145/1046192.1046220

Z. Marrakchi, H. Mrabet, E. Amouri, and H. Mehrez, Efficient Tree Topology for FPGA Interconnect Network, ACM GLSVLSI, pp.321-326, 2006.
URL : https://hal.archives-ouvertes.fr/hal-01301523

A. Rahman, S. Das, A. Chandrakasan, and R. Reif, Wiring Requirments and Three-Dimensional Integration of Field Programmable Gate Arrays, SLIP ACM, 2001.

K. Siozios, A. Bartzas, and D. Soudris, Architecture Level Exploration of Alternative schmes Targeting 3D FPGAs: A Software Supported Methodology, Intern' Journal of Reconfigurable Computing, 2011.