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Article Dans Une Revue Bell Labs Technical Journal Année : 2009

A fast hierarchical arbitration scheme for multi-tb/s packet switches with shared memory switching

Résumé

One challenge in multi-terabit per second packet switches is the design of low latency and high performance arbitration schemes. In this regard, we propose a hierarchical multi-cell arbiter, which interconnects multiple parallel processing devices. By comparison with iterative non-hierarchical multi-cell arbiters, we show that our scheme significantly decreases the signaling overhead and arbitration processing time. Performance evaluation results show the proposed solution maximizes the switch throughput and delay performance.

Dates et versions

hal-00764415 , version 1 (13-12-2012)

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Daniel Popa, Georg Post, Ludovic Noirie. A fast hierarchical arbitration scheme for multi-tb/s packet switches with shared memory switching. Bell Labs Technical Journal, 2009, 14 (2), pp.23-28. ⟨10.1002/bltj.20374⟩. ⟨hal-00764415⟩
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