Towards an unified IP verification and robustness analysis platform

David Hely (1) , Vincent Beroulle (2) , Feng Lu (2) , Jose Ramon Garcia Oya (2)

1 CTSYS - Conception et Test de SYStèmes embarqués
2 LCIS - Laboratoire de Conception et d'Intégration des Systèmes

Mots clés: Fault Injection; Robustness; IC design; FPGA; Verification

Domaines: Micro et nanotechnologies/Microélectronique

David Hely, Vincent Beroulle, Feng Lu, Jose Ramon Garcia Oya. Towards an unified IP verification and robustness analysis platform. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, Apr 2011, France. ⟨hal-00593524⟩