An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

Balkaran Gill (1) , Michael Nicolaidis (2) , Francis Wolff (1) , Chris Papachristou (1) , Steven Garverick (1)

1 Electrical Engineering and Computer Science Department - Case Western Reserve University
2 iRoC Technologies

In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. This BICS found to be very reliable for process, voltage and temperature variation and under stringent noise conditions.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Balkaran Gill, Michael Nicolaidis, Francis Wolff, Chris Papachristou, Steven Garverick. An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. DATE'05, Mar 2005, Munich, Germany. pp.592-597. ⟨hal-00181657⟩