Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

Georges Gielen (1) , Wim Dehaene (1) , Phillip Christie (2) , Dieter Draxelmayr (3) , Edmond Janssens (4) , Karen Maex (5) , Ted Vucurevich (6)

1 K.U. LEUVEN
2 Philips
3 Infineon Technologies AG [München]
4 STMicroelectronics
5 IMEC
6 Cadence

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Georges Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, et al.. Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?. DATE'05, Mar 2005, Munich, Germany. pp.36-42. ⟨hal-00181492⟩