Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL

R. Gascon (1) , Frédéric Mallet (1) , Julien Deantoni (1)

1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) provides a means to specify embedded systems. The Clock Constraint Specification Language (CCSL) allows the specification of causal, chronological and timed properties of MARTE models. Due to its purposedly broad scope of use, CCSL has an expressiveness that can prevent formal verification. However, when addressing hardware electronic systems, formal verification is an important step of the development. The IEEE Property Specification Language (PSL) provides a formal notation for expressing temporal logic properties that can be automatically verified on electronic system models. We want to identify the part of MARTE/CCSL amenable to support the classical analysis methods from the Electronic Design Automation (EDA) community. In this paper, we contribute to this goal by comparing CCSL and PSL expressiveness. We show that none of these languages is subsumed by the other one. We identify the CCSL constructs that cannot be expressed in temporal logics and propose restrictions of these operators so that they become tractable in temporal logics. Conversely, we also identify the class of PSL formulas that can be encoded in CCSL. We define translations between these fragments of CCSL and PSL using automata as an intermediate representation.

Domains: Formal Languages and Automata Theory [cs.FL]

R. Gascon, Frédéric Mallet, Julien Deantoni. Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL. [Research Report] RR-7459, INRIA. 2011. ⟨inria-00540738v2⟩