Energy Consumption Analysis of Software Polar Decoders on Low Power Processors

Adrien Cassagne (1, 2, 3) , Olivier Aumage (1, 4) , Camille Leroux (2) , Denis Barthou (1) , Bertrand Le Gal (2)

1 STORM - STatic Optimizations, Runtime Methods
2 IMS - Laboratoire de l'intégration, du matériau au système
3 UB - Université de Bordeaux
4 LaBRI - Laboratoire Bordelais de Recherche en Informatique

This paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems. A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps. Some design guidelines are given in order to adapt the configuration to the application context.

Mots clés: Decoding Algorithms; Energy Consumption; Throughput; Bit error rate; Program processors; Encoding

Domaines: Calcul parallèle, distribué et partagé [cs.DC]; Traitement du signal et de l'image [eess.SP]

Adrien Cassagne, Olivier Aumage, Camille Leroux, Denis Barthou, Bertrand Le Gal. Energy Consumption Analysis of Software Polar Decoders on Low Power Processors. The 24nd European Signal Processing Conference (EUSIPCO 2016), Aug 2016, Budapest, Hungary. ⟨10.1109/EUSIPCO.2016.7760327⟩. ⟨hal-01363975⟩