Stability oriented SRAM performance optimization in subthreshold operation

Adam Makosiej (1) , Olivier Thomas (2) , Andrei Vladimirescu (3) , Amara Amara (1)

1 MINARC
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 MINARC

In this work we are analyzing the 6T SRAM cell operation in subthreshold in 32nm UTBB-FDSOI technology. The set of accurate equations describing the subthreshold SRAM cell behaviour in read and write are presented. Using these equations, the optimum tradeoffs between cell transistors VTs for best stability in subthreshold for read and retention are illustrated revealing write stability as the main limiting factor for low VDD operation. The analysis of write assist technique efficiency reveals, that setting the bitline voltage -0.1V gives the write μ/σ=5.66, while maintaining read μ/σ>9. The magnitude of write assist technique application can be further limited by modifying the VTs of SRAM cell transistors by increasing initial write stability while maintaining read μ/σ>6.

Domaines: Electronique

Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara. Stability oriented SRAM performance optimization in subthreshold operation. 2011 Subthreshold Microelectronics Conference, Sep 2011, Lexington, Massachussets, United States. pp.32. ⟨hal-00643918⟩