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Communication Dans Un Congrès Année : 2011

Variability-aware Task mapping strategies for Many-cores processor chips

Résumé

The advent of the Deep Submicron technology opens the way to many-cores processor chips. However, the variability and reliability of these processes poses new challenges. In particular, the mapping of applications will require specific strategies to leverage the plenty and diversity of the computation cores. In this regard, generic task mapping strategies are proposed to improve the energy efficiency of the applications, and compared for a synthetic application. In this contribution, we consider Streaming applications (e.g. video, audio or radio), which are modelled as fork-join Directed Acyclic Graph (DAG) of tasks. The Nearest node mapping strategy is used as a baseline, and minimizes the communication overhead. Then, a novel energy criterion is introduced to balance the computation and communication energy consumption. While increasing the communication energy, this strategy reduces the overall consumption by up to 20%. Finally, a mapping strategy based on variability regions improves slightly the energy efficiency of the application in the presence of systematic variations.

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Dates et versions

hal-00624244 , version 1 (16-09-2011)

Identifiants

  • HAL Id : hal-00624244 , version 1

Citer

F. Chaix, G. Bizot, M. Nicolaidis, Nacer-Eddine Zergainoh. Variability-aware Task mapping strategies for Many-cores processor chips. Workshop on Design for Reliability and Variability (DRVW'11), May 2011, Dana Point, CA, United States. ⟨hal-00624244⟩

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